Finally some progress. There simple shapes on display.
This is a second part of longer series where I try to show you interesting stuff about reverse engineering and latest electronics technology.
Sorry for the camera quality. If there will be more interest during this series. I’ll try to find better recording equipment.
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1:50
Normal person: so what?
Guy who spent three weeks getting that: f*ck yeah!
https://youtu.be/VQYZAbMiM4I
thank you 🙂
I'm new to VHDL and the other day I manage to get VGA to work with CPLD. Now with new FPGA I want to get closer to metal and You helped me a lot. Thanks.
Nejsem žádný expert na FPGA ani VHDL, ale zběžný pohled do tvého HDL na githubu zjevně ukazuje, že celý design honíš na stejném kmitočtu, jako LVDS výstupy. To je nelogická blbost. Pouze LVDS výstupy musí jet rychlé, zbytek designu na 1/7 kmitočtu (LVDS serializuješ poměrem x7, nepletu-li se). Pixel clock FullHD panelu bude někde okolo 150MHz, což pravda, je docela dost, ale to LVDS ti musí běžet x7 rychleji, repspektive x3.5 (máš zvlášť linky pro půlky panelu), tj zhruba na 500mbps.
nice work anyway, I've read your code (lvds_test.vhd) on GitHub, what is the output frequency of clkPLL (line 184) in Hz ? is there filcker on your display because of slow speed LVDS transmission rate ?
I wonder how much calculation power the board needs to control that screen. Maybe we could use fast MCU board for that too
Nice video, can i used old laptop inverter with v56 controller board ? how to make it more bright ? or to increase mV of the Inverter ?
Cool man & good luck
This guy made a tiny fpga board as big as rpi0, it could be useful to you
https://youtu.be/6PU7TAN40Jk
Bude někdy pokračování?
My hp laptop 530 inverter not working and laptop working still 2 second and and automatic off
Nice, is it work to LCD TV panel, which is use LVDS, too?
Great job.
不错,要是给予basys2就好了
Very cool! Congrat and keep it up!!
Ok, I was getting excited to see the whole process, but it has turned into a demonstration. So, I say, "Well done" getting it to work.